Power supply utilizing improved voltage regulation

ABSTRACT

A high efficiency, AC-to-DC power supply is provided in which a preregulator circuit including a rectifier bridge is coupled to an AC supply input. Two switching rectifiers, one in each of two arms of the bridge, are controlled by a preregulator control circuit for regulating the turn on time of the bridge and thus the DC output level thereof. An inverter circuit is coupled to the output of the bridge for converting the DC output therefrom to an AC signal with a frequency substantially higher than the AC supply input and with an amplitude dependent on the DC output level of the bridge. The output of the inverter circuit is coupled by a transformer to a rectifier circuit for developing a DC output dependent on the amplitude of the AC signal from the inverter circuit. A flux sensing circuit is coupled to the transformer for developing a feedback control signal dependent on the transformer flux density. The preregulator control circuit includes means responsive to this feedback control signal for controlling the turn on time of the switching rectifiers to thereby control the DC level at the bridge output and maintain a constant flux density in the transformer. In addition, the power supply includes means responsive to the load current for controlling the gain of the feedback loop to maintain a stable loop with fast response time.

United States Patent Oliver 1 1 Sept. 11, 1973 [57] ABSTRACT A highefficiency, AC-to-DC power supply is provided [75] Inventor: Bernard M.Oliver, Los Altos Hills, in which a preregulator circuit including arectifier Calif. bridge is coupled to an AC supply input. Two switching'13 Assignee: Hewlett-Packard Company, Palo i g' each f f f Alto Califcontro e y a preregu ator contro c1rcu1t or regu atmg the turn on timeof the bridge and thus the DC out- [22] Filed: May 15, 1972 put levelthereof. An inverter circuit is coupled to the output of the bridge forconverting the DC output 1 Appl N therefrom to an AC signal with afrequency substantially higher than the AC supply input and with an am-[52] US. Cl 321/2, 321/18, 321/47 plitude dependent on the DC outputlevel of the bridge. [51 Int. Cl. H02m 7/20 The output of the invertercircuit is coupled by a trans- [58] Field of Search 321/2, l6, 18, 19,former to a rectifier circuit for developing a DC output 321/47dependent on the amplitude of the AC signal from the v inverter circuit.A flux sensing circuit is coupled to the [56] References Citedtransformer for developing a feedback control signal 1 TE STATES PATENTSdependent on the transformer flux density. The prere'g- 3,413,53811/1968 Hodges 321/2 control meaqs respons've to 3,185,912 /1965 Smithet a]. 32mg feedback control signal for controllmg the turn on time3,218,540 11/1965 Jackson 321/18 of the Switching reclifiers to therebyControl the DC 3,305,763 2/1967 Kupferberg et al 321/18 x level at thebridge Output and maintain a constant flux 3,320,512 5/1967 Kruger .5321/19 X density in the transformer. In addition, the power sup-3,437,905 4/1969. He aley et a1 321/19 ply includes means responsive tothe load current for controlling the gain of the feedback loop' tomaintain a Primary ExaminerWilliam M. Shoop, Jr. stable loop with fastresponse time. Attorney-Roland l. Griffin 1 9 Claims, Drawing Figuresiii 42. 211 pm 42.211 RN 7 E FILTER 3/ 3a Fl 01 115/230 AC 1 D2 --1. c2-23: 36L] 03 35 I '1T '1 @iKW'T R1 2m 7 1 z Acc F I 34\ 2 m1 .OFHIFD ICZ D9 47K IR 9900 1.3 R2 IKV f R5 c I 4d }9o.9v

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PATENTEB 1 3 SHEEI 5 OF 5 POWER SUPPLY UTILIZING IMPROVED VOLTAGEREGULATION BACKGROUND O THE INVENTION Power supplies for convertingstandard supply line voltages at ll-230V AC and 50-60Hz to a pluralityof DC voltage outputs for use with electronic equipment utilizingtransistors and integrated circuits, for example computers, are incommon use. As an example, a computer may require either positive ornegative DC voltages at 2, 5, I2, and volts and currents ranging from100 ma to 60 amps. These output voltages must be well regulated, and thepower supply for the computer must operate from the standard AC supplyline voltage subject to the usual type of random variations.

In one form of such power supply, the AC input volt- A age is firstconverted to a DC output voltage level by a preregulator circuitincluding a full wave rectifier bridge. This DC output voltage is thenconverted by an inverter circuit into an AC voltage at a frequencysubstantially higher than the frequency of the supply line voltage. Aplurality of separate rectifier circuits coupled to the AC output of theinverter circuit via a coupling transformer provide the desired multipleoutput DC voltage outputs. Certain of these DC voltage outputs may beadditionally converted by regulators such as switching regulators tofurther DC'voltage outputs.

In these power supplies it is very important to maintain good regulationof the several DC voltage outputs with varying supply line and outputload conditions.

SUMMARY OF THE INVENTION In the power supply incorporating the presentinvention, the rectifier bridge utilized in the preregulator circuitincludes controlled switches, such as silicon controlled rectifiers(SCRs), in two of the arms of the bridge. The turn on time of these twoSCRs is controlled from a preregulator control circuit to establish thedesired voltage level output from the rectifier bridge. a

In orderto control the SCR's of the rectifier bridge such that theseveral regulated DC voltage outputs are maintained with goodindependence from supply line and/or load variations, it is possible tomeasure the load current changes at one of the several DC voltageoutputs and control the SCR turn on times in dependence thereon;however, regulation at the remaining DC voltage outputs would not beoptimum. In the present invention,.a novel flux sensing technique isemployed to sense the flux density in the coupling transformer for theinverter circuits, and the flux changes are converted to an errorfeedback signal to control the turn on time of the SCR's and thusregulate the DC output voltage level of the rectifier bridge constantflux denfrequency response over the entire range of load currentvariations.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a powersupply incorporating the present invention.

FIG. 2 is a schematic diagram of the preregulator circuit stage of thepower supply.

FIG. 3 is a block diagram of the inverter circuit stage of the powersupply.

FIG. 4 is a schematic diagram of one of the inverter circuits of FIG. 3.

FIG. 5 is a schematic diagram of one of the inverter driver circuits ofFIG. 3.

FIG. 6 is a schematic diagram of one of the rectifier circuits of thepower supply.

FIG. 7 is a schematic diagram of the preregulator control circuit of thepower supply.

FIG. 8 shows traces illustrating the relationship between the firingangle of the SCRs in the preregulator circuit of FIG. 2 and the voltagelevel of the input waveform.

FIG. 9 shows traces illustrating the charge time of the capacitor in theintegrator circuit of the preregulator control circuit of FIG. 7.

FIG. '10 illustrates the timing pulses in the preregulator controlcircuit of FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, the powersupply comprises a preregulator circuit 11 including a rectifier bridgeconnected across the 60Hz 1 l5 volt supply line 12 and producing a DCvoltage output at, for example, 160 volts. The bridge includes two SCRsand two diodes, and a choke and capacitor in the output loop. A controlcircuit ll'for controlling the turn on time of the SCR's dependent onthe level of the supply output voltage and thus regulating the DC outputlevel, is included in the preregulator circuit. In addition, two othercontrol functions are provided in SCR control circuit 11'; onecompensates for variations in input line voltage by changing the SCRtrigger time in accordance with the line voltage, and the othercompensates for load current variations by changing the gain of thefeedback loop in accordance with load current changes.

The output of the preregulator 11 is transmitted to a pair of invertercircuits l3 and 14 each converting the DC input voltage to a square waveAC output at a frequency substantially higher than the 60I-Iz linefrequency, for example 800I-Iz, as determined by clock 15. The squarewave outputs of the two inverters l3 and 14 are out of phase by so thatthe half-wave of one overlaps the commutation interval of the other andvice versa. I

These two inverter outputs are then converted to the desired output DCvoltage levels by a rectifier circuit 16 including a pair oftransformers I7 and 18. One of these output voltage levels is convertedto a different output voltage level by a ZOKHz switching regulatorcircuit 19, and another is converted to a different voltage level bymeans of a series-shunt regulator 19'.

A flux sensing circuit 20 associated with the transformers I7 and 18transmits a signalrelatedto flux change to the preregulator circuit tocontrol the SCR turn on and thus regulate the flux in transformers l7and 18. A separate power supply 21 provides the voltages necessary forthis system.

Referring to FIG. 2, the preregulator circuit comprises an SCR bridgeconnected across the supply line, which may be 115 or 230 volts AC,double fused at F1 and F2 because of the high current drain. An RFlfilter 31 is provided in the lineto guard against RF transients feedingback into the line from the SCR switching bridge and to keep linetransients from disrupting the supply. Because of the high currentvalues, a relay switch 32 is utilized to establish the energizedcondition for the system. Capacitors C1, C2 and C2 are included for thepurpose of containing any current surges in the bridge loop due to theswitching SCRs.

The bridge circuit comprises two SCRs D1 and D2 in the two arms thereofconnected to one side 33 of the incoming line and two diodes D3 and D4in the other two arms connected to the other side 34 of the incomingline. The output terminals 35 and 36 of the bridge are coupled via afirst inductor winding L1, two series connected capacitors C3 and C4,and a second inductor winding L2, the two inductor windings L1 and L2being wound on the same core so as to be mutually coupled and beinginterconnected so as to be aiding around the loop 35, L1, C3, C4, L2,and 36. A switch or strapping arrangement 37 is provided so that thelower input bridge terminal 34 may be connected to the midpoint of thetwo capacitors C3 and C4 for operation from a 1 volt input line. For 230volt input line operation, the strapping 37 is removed.

The operation of this bridge circuit is as follows for 230 voltoperation with the strap 37 removed. During the positive half cycle, SCRD2 is turned on by a pulse at gate 38 via the gate control circuitincluding transformer T1, and current flows through diode D2, inductorLl, capacitors C3 and C4, inductor L2, and diode D3 to the other side ofthe line. Because of the mutual inductive coupling, and aidinginterconnection, the inductance around the loop is approximately fourtimes the inductance of the individual coils. During the negative halfcycle, SCR D1 is turned on and the current flows thrugh the loopincluding diode D4. By straightforward bridge rectifier action, a fullwave rectified voltage appears at line 39 with a DC value of 0.636 timesthe voltage peak of the incoming wave, i.e., about 206 volts for the 230volt AC input when the SCR's are turned on at the beginning of eachhalf-cycle. The firing angle is adjusted by the feedback control loopincluding SCR control circuit 11 (see FIG. 1) in such a manner as tohold the output to 160 volts DC.

For the l 15 volt input line operation, a voltage doubling is providedby this bridge circuit. The strap 37 is established and, during thepositive half-cycle of the incoming signal, the current loop is tracedthrough SCR D2, inductor Ll, capacitor C3 to the low line terminal 34 ofthe bridge via strap 37.. For the negative halfcycle, the circuit istraced from the lower line 34 through the capacitor C4, inductor L2 anddiode D1 to the upper side of the line. Duringthe time that current isflowing through C3, the voltage drop across Ll also appears across L2due to the mutual inductive coupling, and this voltage back biasesdiodes D1 and D3 so that no current can flow in L2 during the positivehalfcycle. During the negative half-cycle D1 conducts current through L2charging C4 and the voltage drop across L2 appears across L1 and backbiases diodes D2 and D4. a

The energy stored in one inductor during one halfcycle is transferred tothe other inductor due to the mutual inductive coupling during the nexthalf-cycle to thereby cause the current in the other inductor to rise toa value twice as great as in the bridge operation on the 230 volt inputline. Thus, a forced voltage doubling action takes place in the voltinput line case, and the output line 39 is maintained at the controlledlevel of 160 volts.

So that the current in the output loop of the bridge will never drop tozero during the commutation intervals when the input wave form is goingfrom positive to negative or vice versa, the inductors L1 and L2 must beof such a size that the energy stored in each is sufficient to maintaincurrent flow during the half-cycle when no current is supplied to therespective capacitor from the supply line.

For any given value of load resistance, a value of critical inductancecan be specified for maintaining this continuous current flow. However,with the high voltage and current requirements for this circuit,maintaining critical inductance values for L1 and L2 requires aninductive structure L1 and L2 of large size and weight. When employingan inductive structure of a smaller size and weight, the inductancevalues of L1 and L2 fall below the critical value and the end result isthat, during the commutation periods, the current in the inductors isdepleted and the load current is maintained by a discharge from thecapacitors C3 and C4, thus producing a larger ripple voltage on theoutput line 39.

A ripple reduction circuit is provided which operates to both double thefrequency of the ripple voltage and, at the same time, significantlyreduce the peak-to-peak voltage of the ripple, thus providingsubstantialy improved regulation and reduced ripple while stillpermitting the use of inductors L1 and L2 of substantially reduced sizeand weight. This ripple reduction circuit comprises a tap 4l in theinductor Ll, the inductor L3 and the capacitors C5 and C6 across theoutput line. Two capacitors are used in lieu of one solely for thepurpose of obtaining a higher capacitance value with two components moreeasily fitted within the power supply package.

With the tap in inductor Ll, a small voltage signal is obtained whichresembles the wave form at terminal 35, and this voltage is added inseries with the ripple at the junction of inductor L1 and capacitor C3.The phase of this small voltage is such that it sums with the lineripple to, in effect, fill in the valley portions of the cycle ripple.This produces a wave form on the output line 39 at a frequency of 240 Hzwith a peak-topeak amplitude about one half the value of the ripplevoltage at the junction of inductor L1 and capacitor C3. This higherfrequency ripple is more easily filtered by the inductor L3, which issubstantially smaller than the inductor that would be needed with aripple frequency of l20Hz. A resistor R1 connected across the inductorL3 serves to lower the Q to avoid any resonances therein. Thus theeffect of undesired ripples generated on the volt line by the use of asignificantly smaller inductive structure L1 and L2 is compensated bydoubling the ripple frequency and cutting the peak-to-peak amplitude bya significant factor, for example one fourth, at the output line 42. Bythis technique it has been possible to reduce the value of inductors L1and L2 from about 50 millihenrys to about 7 to 8 millihenrys whilemaintaining the same size capaci tors C3 and C4. Inductors Ll and L2 arechosen to limit the value of peak current flowing in the primarycircuit.

A crowbar circuit comprising the SCR D5, a resistor R2, diodes D6 andD7, and resistors R3 and R4 is included for the purpose of power supplyand load protection. The two diodes D6 and D7 have values such that thevoltage threshold is set at about I80 volts as an upper trip limit.Should the 160 volt line 42 attempt to exceed the 180 volt drop of D6and D7, the gate of the SCR D5 is turned on. SCR D5 acts to pull the 160volt line 42 down rapidly. Resistor R2 serves to limit the peak currentin SCR D5. In addition, the gate of SCR DS can be controlled via diodeD8 and transformer T2 from a voltage or current sensing circuit in theload circuit of the system. In addition to the crowbar circuit, thebridge may also be turned off by interrupting the flow of gate pulses tothe gates of the SCRs D1 and D2 via the transformer T1 from thepreregulator control circuit described more fully below.

The resistors R5 and R6 are provided across the capacitors C3 and C4 forthe purpose of discharging the capacitors within a reasonable period oftime, for example 1 minute, so that the circuit may be safely worked onafter it is turned off.

Diodes D9 and D10 are provided across the capacitors C3 and C4 toprotect these capacitors during the crowbarring of the 160 volt outputline 42 by D5. Because of the tolerances in the values of C3 and C4, oneof these capacitors may be larger than the other by a significantamount. Therefore, during pulldown of the output line 42, the smallercapacitor depletes-much faster than the larger capacitor, and the netresult, when a zero voltage is reached between the high line 42 and thecommon line 43, would be a voltage at the circuits generate square wavevoltages that are displaced by 90 with respect to each other. This 160line 42 is connected to terminal 44, and the common line 43 is connectedto terminal 45 of the inverter circuit. This bridge type circuitcomprises four switches Q1, Q2, Q3, and Q4 with their bases connected tothe sec ondary windings 46, 47, 48 and 49, respectively, associated withthe primary winding 51 of transformer T3 in the inverter driver (seeFIG. 5). The inverter driver circuit of FIG. 5 comprises a pair'of totempole driver circuits with the primary of transformer T3 connected acrosstheir outputs. The base drive for transistors Q5 and O6 in the totempole" drivers is obtained from a clock source, e.g., 800Hz. When Q5 ison, O7 is off and current flows through-diode D11 and the collector ofQ5 to ground. O7 is held .off by the diode drop. When 05 is turned off,the voltage at the collector goes high, taking the base of Q7 up, and Q7performs like an emitter follower bringing the left hand side of thetransformer winding 51 high. The two totem pole driver circuits operatealternately to reverse the polarity across the primary transformerwinding 51 at the 800 cycle rate thereby energizing the four secondarywindings 46-49v at the same frequency rate.

The switches Q1 and Q4 of the inverter circuit of FIG. 4 conduct duringone time interval of the cycle and the other two switches Q2 and Q3conduct during the other time interval. Thus, a substantially squarewave output at 80OHz appears on the two secondary windings, 52 and 53 ofthe transformer T4. Actually, the wave form is not a true alternatingsquare wave but is provided with a very slight idle or dead timeinterval during the commutation so that transistor pairs Q1, Q2 and Q3,Q4 will not be turned on at the same time, which would result in acurrent path across the line directly through two series-connectedtransistors, resulting in serious damage. The slight delay time isprovided by the clock pulses to the base drive of Q5 and O6 in theinverter driver circuits. I

There are two inverter circuits in this system and they are operated 90out-of-phase so that the full wave output of one inverter circuitoverlaps the idle or dead interval between the two half-cycles of theother inverter output wave form. This insures that the combined fullwave rectified output will not have depressed or valley portions betweeneach half-cycle. If one were to operate single phase and provide afilter circuit to remove Y the depression between the half-cycle, itwould take a very large inductor capacitor circuit because of the veryhigh currents provided with this power supply. By overlapping the twophase outputs, it is not necessary to provide large capacitors andpractically pure DC level is obtained without or with very littlefiltering. There is very small step-down in the output voltage levelwhere each idle period appears in the output wave form of the twoinverters, but this is of minor consequence. By going to this two phasesystem in lieu of a large amount of capacitor filtering, the amount offilter capacitance needed on all of the power outputs has been reducedand the size and the weight of the power supply substantially reduce.Although the circuitry for an added inverter and inverter driver,including its transformer, has been added, the overall savings in sizeis very significant.

Referring to FIG. 6, the primary winding of each inverter circuittransformer T4 and T4 is coupled to a pair of secondary windings 52, 53and 52', 53', respectively, each being center tapped and also having aplurality of taps to provide the desired voltage output levels. This twophase, full wave rectification provides a pluraltiy of separate DCvoltage level outputs, for example 30.0 volts, 12.0 volts, 5.0 voltsand,2.0 volts. As noted above, becausethe two phase operation providesfill in between the individual half wave segments, relatively smallinductors L4a-d may be used in the output filter circuits.

One of the 30 volt DC outputs is coupled to the input of a switchingmode regulator circuit 19 (see FIG. '1) to obtain a regulated voltageoutput adjustable between, for example, 18.5 volts and 24.5 volts. A 20Voutput is obtained from another 30V line via regulator circuit 19.

A preregulator control circuit shown in FIG. 7 is provided to generatean output function such that, should the supply line voltage change, thefiring angles of the two SCRs D1 and D2 in the input bridge circuitchange by a time increment just sufficent to hold the DC level output ofthe bridge constant. This provides a first regulation of the outputline. Precise control of the output voltage is provided by the novelflux sensing technique described below.

The traces in FIG. 8 illustrate the'relationship bevoltage level of theinput wave form needed to maintain a constant voltage level output fromthe bridge circuit of, for example 160 volts. It is seen that, for'a lowlevel input line voltage represented by curve A, a firing anglerepresented by point A is required whereas with a high level of inputvoltage represented by line' B a different firing angle B is dictated. Ameans of developing the proper triggering time in response to linevoltage is given below.

The input voltage is supplied through transformer T to a full waverectifier circuit 66 which produces a rectified wave form output at 67as shown in FIG. 10a. A similar current wave form passes into theemitter of Q13 of an integrator circuit including the capacitor C7. Theamount of current passing to C7 may be controlled by means of Q14. Thecharge on capacitor C7 rises as shown in FIG. 9 during the half-cycleperiod. A reset pulse on the base of Q15 from the pulse timing generatorat about the zero point in the full wave rectified wave form resets theintegrating circuit, and the voltage at the collector of Q15 drops to alow value. Resistor R10 limits the capacitor discharge current. Thecollector volage of Q15 drops to the point where Q15 is saturated, andit remains saturated for a short period until the base of Q15 is turnedoff and the voltage at the collector rises and the integration cyclebegins again.

It is desired that the base level of this wave form be established atthe peak point of the integration curve and that the lower level of thisvoltage wave form be allowed to vary in accordance with the line voltagevariance. In this manner, the lower level will vary in directrelationship to the voltage level of the input line, a high inputvoltage giving a greater voltage excursion for the integrated wave formthan a lower input voltage. Establishment of the base level at the topof the integrated wave form is provided by the DC restor'er circuitcomprising the FET switch Q16 which operates on each half-cycle toestablish the right-hand side of capacitor C8 at ground level just priorto reset of the integrator. The FET switch Q16 is turned on and off by apulse from the pulse timing generator just prior to delivery of thereset trigger pulse to Q15.

The pulse timing generator comprises the circuit shown in the dottedline enclosure. This circuit operates from the input wave form (see FIG.10a) at the base of Q17 to produce a rectangular wave form (see FIG.10b) at the base of Q18, a reset pulse (see FIG. 100) at the collectorof Q19 used to operate the FET switch Q16, and a reset signal (see FIG.10d) at the collector of Q20 that has an initial ramp portion buildingsource for the differential amplifier stage. The voltage on the input ofthe input FET Q21 of the differential amplifier is compared with theamplified feedback voltage applied to FET Q22 from a differentiailamplifier 68. When the input level to the FET Q21 reaches the voltageestablished at the gate of FET Q22, the flip-flop circuit Q23 and Q24 isoperated to produce a square pulse output. The width of the output pulseis dependent on the time interval between the comparator levelcross-over and the integrator reset, which time interval is in turndependent on the voltage level of the input line to the gate of FET 022.

The output of the flip-flop Q23 and Q24 is coupled to a blockingoscillator circuit which includes the transistor Q26, the output of theflip-flop being coupled to the oscillator via resistor R13 and diodeD14. When the left-hand side of R13 is elevated above l5 volts by about3 volts, current flows through diode D14, developing a voltage dropacross resistor R13. A portion of the current flows through thebase-emitter junction of Q26, causing it to conduct and pass currentthrough the primary winding of transformer TI. This initiates a seriesof pulses from the blocking oscillator Q26. The secondary windings ofthe transformer T1 are the SCR gate control windings shown in FIG. 2.

This blocking oscillator works in a regenerative fashion to produce aseries of output pulses for the interval that the flip-flop Q23 and Q24is on, i.e., as long as a high input appears at the base of transistorQ26. The time of initiation of this series of pulses is dependent on thewidth of the pulse generated by the flip-flop and is thus dependent onthe amplitude of the input voltage applied to the gate of FET Q22. Aseries of trigger pulses is provided rather than a single SCR gatingpulse to insure that, should the SCR not be in condition to be triggeredor turned on upon receipt of the first trigger pulse, it will be turnedon at the first opportunity by a subsequent pulse in the trigger pulseseries. This insures that the bridge circuit will not miss a cycle ofoperation in the AC rectification.

Provisions are made to enable the turn-off of the SCR trigger pulses sothat the regulator operation may be terminated. IN one case, either a l5 volt off" voltage or +15 volt on" voltage may be connected to theinput of Q23 transistor. In another instance, control may beaccomplished by a +15 volt off" voltage or a l5 on voltage at the gateof FET Q22.

The gain of this system may be regulated in response to an input voltagederived from the load current and applied to the base of multiplier Q14,which multiplies the input voltage at input 69 by the current derivedfor the integrator circuit from the input transformer T5. This inputvoltage serves to direct current flow between the two transistors Q13and Q14 and thus regulates the current flow into the integratorcapacitor C7. The multiplier control voltage is derived from loadcurrent sensing circuits comprising current transformers T6 and T6 andthe associated rectifiers D16 and amplifier circuit 71 (see FIG. 4).Current transformers T6 and T6 are connected in series with theprimaries of the inverter transformers T4 and T4, respectively.

The amplifier 71 provides an output voltage which is a function of thetotal load current being delivered to the load. As the total loadcurrent increases, the output of amplifier 71 increases to therebyincrease the voltage on the base of transistor Q14, causing less currentto flow through transistor Q14 and more current to flow throughtransistor Q13 to the capacitor C7. This capacitor charges up morerapidly and thus the magnitude of the waveform appearing at the input tothe comparator amplifier Q21 and Q22 is multiplied, adjusting the gaincrossover of this regulation loop to maintain a stable loop with fastresponse. A decreasing load current will result'in less current throughtransistor Q13 and a reduction in the gain to maintain an optimum gaincrossover. Thus, fast response time is maintained and a stable loopobtained over a wide range of load current variation.

The input signal fed back to the preregulator control circuit to controlthe differential amplifier 68, and thus control the firing time of theSCRs D1 and D2, could be obtained from one of the output load circuits.This would serve to regulate the output voltage relative to thatparticular output voltage level, but would result in a relatively poorregulation of the other DC output levels. For this reason, a feedbacksignal is derived which is proportional to the flux density of thetransformers T4 and T4 shown in FIGS. 3 and 6. In this embodiment, theflux is sensed with the 30 volt transfomier secondary winding by meansof the flux sensing diodes D15, a separate pair of such diodes beingcoupled to each 30 volt secondary of the two inverter transformers T4and T4". The diodes D15 are poled so as to pass current only when theassociated section of the secondary winding is unloaded, i.e., duringthat half of the cycle when the other section of the secondary windingis cartying the load current. Under this unloaded condition,

the voltage generated across the unloaded secondary is Nd 1 Idt and thefeedback voltage signal is E NdQ/dt E(R secondary winding and R diode)/RV diode. Since, with no current flowing in the circuit, the latter twovalues are relatively small and constant, E k Nd bldt. This feedbackvoltage is thus dependent on Nd l ldt and is compared to the referencevoltage +l5V by resistor network R14 and R15, thus generating an errorsignal at the input to amplifier 68.

The output of amplifier .68 changes the level of comparison at the inputof comparator Q21 and Q22 in 'such a manner as to adjust the firingangle of the S'CRs D1 and D2 as described above. Thus the flux in theinverter transformers T4 and T4 is maintained constant, insuring goodoutput line regulation.

o'nJan. 29, 1973.

What is claimed is:

1. A DC power supply for converting AC voltage on an input supply lineto a plurality of separate DC voltages, said DC power supply comprising:

a 'rectifierbridge circuit including controlled rectifier switches,having an input connected across the input supply line, and beingoperable'for producing a DC voltage at an output of the rectifier bridgecircuit;

a first inverter circuit coupled to the output of the rectifier bridgecircuit for receiving the DC voltage produced by the rectifier bridgecircuit;

drive means coupled to the first inverter circuit for operating it at aselected alternating rate substantially higher than the alternating rateof the AC voltage on the input supply line to produce an AC voltage atan output of the first inverter circuit;

an output rectifier circuit including a first transformer and beingcoupled to the output of the first inverter circuit via the firsttransformer for converting the AC voltage produced by the first invertercircuit to a plurality of separate DC voltages provided at a pluralityof separate outputs of the output rectifier circuit;

flux sensing means for sensing the flux in the first transformer; and

a control circuit coupled to the controlled rectifier switches andresponsive to the fiux sensed in the first transformer for controllingthe turn-on time of the controlled rectifier switches and therebymaintaining a constant flux density in the first transformer to regulatethe DC voltages provided at the outputs of the output rectifier circuit.

2. A DC power supply as in claim 1 wherein said flux sensing meanscomprises:

means coupled to a secondary winding of the first transformer forsensing the voltage across the secondary winding in the unloadedcondition with no load current flowing therein; and

means for producing a feedback signal from the voltage sensed across thesecondary winding of the first transformer to control the turn-on timeof the controlled rectifier switches.

3. A DC power supply as in claim 1 wherein:

said DC power supply includes a second inverter circuit coupled to theoutput of the rectifier bridge circuit;

said drive means is coupled to the second inverter circuit for operatingit at the selected alternating rate to produce an AC voltage at anoutput of the second inverter circuit, the AC voltage produced at theoutput of the second inverter circuit being outof-phase with respect tothe AC voltage produced at the output of the first inverter circuit;

said output rectifier circuit also includes a second transformer and iscoupled to the outputs of both the first and second inverter circuitsvia the first and second transformers, respectively, for converting theAC voltages produced by the first and second inverter'circuits to the DCvoltages provided at'the output of the output rectifier circuit;

said flux sensing means is operable for sensing the flux in boththefirst and second transformers; and

said control circuit isresponsive to the flux sensed in both the firstand second transformers for controlling the turn-on time of thecontrolled rectifier switches and thereby maintaining a constant fluxdensity in the first and second transformers to regulate the DC voltagesprovided at the outputs of the output rectifier circuit.

4. A DC power supply as in claim 1 wherein said controlled rectifierswitches are SCRs.

5. A DC power supply for converting incoming AC voltage on an inputsupply line to a plurality of separate output DC voltages for associatedload circuits, said DC power supply comprising:

a preregulator including a rectifier bridge circuit for converting theincoming AC voltage to a DC voltage provided at an output of thepreregulator, said rectifier bridge circuit including controlledrectifier switches;

conversion means coupled to the output of the preregulator forconverting the DC voltage provided at the output of the preregulator toan AC voltage and for subsequently c'onvertingthis AC voltage into aplurality of separate output DC voltages provided at a plurality ofseparate outputs of the conversion means; t

a control circuit for controlling the turn-n time of the controlledrectifier switches and thereby regulating the level of the DC voltageprovided at the output of the preregulator, said control circuitincluding an amplifier and being responsive to changes in the incomingAC voltage for changing the turn-on time of the controlled rectifierswitches; and feedback means coupled to the control circuit andresponsive to load current variations at the outputs of the conversionmeans for providing a feedback signal to adjust the gain of theamplifier and provide optimum gain crossover in the regulation loopcomprising the preregulator, conversion means, and control circuit. 6. ADC power supply as in claim 5 wherein: said conversion means includes afirst inverter circuit, a plurality of full wave rectifier circuitscoupled to the outputs of the conversion means, and a first transformerincluding a primary winding coupled to an output of the first invertercircuit and including a-plurality of secondary windings coupled to thefull wave rectifier circuits; said conversion means further includesdrive means coupled to the first inverter circuit for operating it at aselected alternating rate substantially higher than the alternating rateof the incoming AC voltage on the input supply line to produce an ACvoltage at the output of the first inverter circuit; said power supplyincludes flux sensing means for sensing the flux in the firsttransformer; and said control circuit includes means responsive to theflux sensed in the first transformer for controlling the turn-on time ofthe controlled rectifier switches and thereby maintaining aconstant fluxdensity in the first transformer to regulate the output DC voltagesprovided at the outputs of the conversion means.

7. A DC power supply as in claim 6 wherein said flux sensing meanscomprises:

means coupled to a secondary winding of the first transformer forsensing the voltage across the secondary winding in the unloadedcondition with no load current flowing therein; and

means for producing a feedback signal from the voltage sensed across thesecondary winding of the first transformer to control the turn-on timeof the controlled rectifier switches.

8. A DC power supply as in claim 6 wherein:

said conversion means includes a second inverter circuit, and a secondtransformer having a primary winding coupled to an output of the secondinverter circuit and having a plurality of secondary windings coupled tothe full wave rectifier-circuits;

said drive means is coupled to the second inverter circuit for operatingit at the selected alternating rate to produce an AC voltage at theoutput of the second inverter circuit, the AC voltage produced at theoutput of the second inverter circuit being out of phase with respect tothe AC voltage produced at the output of the first inverter circuit;

said flux sensing means is operable for sensing the flux in both thefirst and second tranformers; and

said control circuit is responsive to the flux sensed in the first andsecond transformers for controlling the turn-on time of the controlledrectifier switches and thereby maintaining a constant flux density inthe first .and second transformers to regulate the DC voltages providedat the outputs of the conversion means.

9. A DC power supply as in claim 6 wherein said controlled rectifierswitches are SCRs.

v mm STATES PATENT owner @ERTIFICATE @F QRREQTEN PatentNou 3,758,840 iDated September ll l973 Inventor (s) Bsrriar'dM. Oliver It is certified"that error appears in" the aboveddentified patent and that said LettersPatent are hereby corrected as shown"below:

Column 1., line 25, after "multiple" delete output line 53, "circuits"should read circuit line 56, after u e tifier bridge." insert tomaintaina desired column line -32 -after- "1115" insert or 230 "line 60, after"different" insert output v Column-3, line 40', "thrugh" should readthrou h; Column line "33) "substantially", sliould read substantially. q7 l 1 Column-5, lin'e 4'5 ,"Th isl6O line 'should read The 160 voltline-5.;

Column 6, line 25, "inductor capacitor" should" readinductor-capacitorline'37', "reduce", should read reduced -'-v;"

Column 7','-' 1.ine 25,"-"volage-" should r ead. voltage"-; line 66,"dif fere ntiail" should readdifferential Columh 8:, line 38, "im"should read In line 40, )"Q23 transistor".should read re transistor Q23Sigusdahd sealed this 25th day of Decemble r l973.

(SEAL Attest: p I a I V EDWARD M.F-LE QHBRQJR. Y RENE D, TEGTMEYERttesting Officer .Acting Commissioner of Patents FORM po'wso uscoMM-ocscan-pas a 0.. 600 0 us, GOVERNMENT PRINTING OFFICE Ian 0 an an UNITEDSTATES PATENT GEHCE CERHHECATE Git QGRRECHQN Patent No 758,840 DatedSeptember ll, 1973 Inv n Bernard M. Oliver It is certified that errorappears in the above-identified patent and that said Letters Patent arehereby corrected as shown' below:

Column 1, line 25, after "multiple delete output line 53, "circuits"should read circuit line 56, after "rectifier bridge" insert. tomaintain a desired Column 2, line 32, after "ll5' insert or 230 line 60,after "different" insert output 7 Column 3, line 40, "thrugh" shouldread through Column 4, line 33, "substantialy" should read substantiallyv Column 5, line 45, "This 160 line" should read The 160 volt lineColumn 6, line 25, "inductor capacitor" should read inductor-capacitor.line 37, "reduce" should read reduced Column 7, line 25, "volage" shouldread, voltage 7 line 66, "differentiail" should read differential Column8, line 38, "IN" should read In line 40, "Q23 transistor"rshould readtransistor-Q23 Signed and scaled this 25th day of December 1973.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. RENE 1).. TEGTMEYER ttesting Officer ActingCommissioner of Patents ORM 2 0-1050 (10-69) v USCOMM'DC 60376-P69 ago 05, GOVERNMENT PRINTING OFFICE I9! 0-3G-33l

1. A DC power supply for converting AC voltage on an input supply lineto a plurality of separate DC voltages, said DC power supply comprising:a rectifier bridge circuit including controlled rectifier switches,having an input connected across the input supply line, and beingoperable for producing a DC voltage at an output of the rectifier bridgecircuit; a first inverter circuit coupled to the output of the rectifierbridge circuit for receiving the DC voltage produced by the rectifierbridge circuit; drive means coupled to the first inverter circuit foroperating it at a selected alternating rate substantially higher thanthe alternating rate of the AC voltage on the input supply line toproduce an AC voltage at an output of the first inverter circuit; anoutput rectifier circuit including a first transformer and being coupledto the output of the first inverter circuit via the first transformerfor converting the AC voltage produced by the first inverter circuit toa plurality of separate DC voltages provided at a plurality of separateoutputs of the output rectifier circuit; flux sensing means for sensingthe flux in the first transformer; and a control circuit coupled to thecontrolled rectifier switches and responsive to the flux sensed in thefirst transformer for controlling the turn-on time of the controlledrectifier switches and thereby maintaining a constant flux density inthe first transformer to regulate the DC voltages provided at theoutputs of the output rectifier circuit.
 2. A DC power supply as inclaim 1 wherein said flux sensing means comprises: means coupled to asecondary winding of the first transformer for sensing the voltageacross the secondary winding in the unloaded condition with no loadcurrent flowing therein; and means for producing a feedback signal fromthe voltage sensed across the secondary winding of the first transformerto control the turn-on time of the controlled rectifier switches.
 3. ADC power supply as in claim 1 wherein: said DC power supply includes asecond inverter circuit coupled to the output of the rectifier bridgecircuit; said drive means is coupled to the second inverter circuit foroperating it at the selected alternating rate to produce an AC voltageat an output of the second inverter circuit, the AC voltage produced atthe output of the second inverter circuit being out-of-phase withrespect to the AC voltage produced at the output of the first invertercircuit; said Output rectifier circuit also includes a secondtransformer and is coupled to the outputs of both the first and secondinverter circuits via the first and second transformers, respectively,for converting the AC voltages produced by the first and second invertercircuits to the DC voltages provided at the output of the outputrectifier circuit; said flux sensing means is operable for sensing theflux in both the first and second transformers; and said control circuitis responsive to the flux sensed in both the first and secondtransformers for controlling the turn-on time of the controlledrectifier switches and thereby maintaining a constant flux density inthe first and second transformers to regulate the DC voltages providedat the outputs of the output rectifier circuit.
 4. A DC power supply asin claim 1 wherein said controlled rectifier switches are SCR''s.
 5. ADC power supply for converting incoming AC voltage on an input supplyline to a plurality of separate output DC voltages for associated loadcircuits, said DC power supply comprising: a preregulator including arectifier bridge circuit for converting the incoming AC voltage to a DCvoltage provided at an output of the preregulator, said rectifier bridgecircuit including controlled rectifier switches; conversion meanscoupled to the output of the preregulator for converting the DC voltageprovided at the output of the preregulator to an AC voltage and forsubsequently converting this AC voltage into a plurality of separateoutput DC voltages provided at a plurality of separate outputs of theconversion means; a control circuit for controlling the turn-on time ofthe controlled rectifier switches and thereby regulating the level ofthe DC voltage provided at the output of the preregulator, said controlcircuit including an amplifier and being responsive to changes in theincoming AC voltage for changing the turn-on time of the controlledrectifier switches; and feedback means coupled to the control circuitand responsive to load current variations at the outputs of theconversion means for providing a feedback signal to adjust the gain ofthe amplifier and provide optimum gain crossover in the regulation loopcomprising the preregulator, conversion means, and control circuit.
 6. ADC power supply as in claim 5 wherein: said conversion means includes afirst inverter circuit, a plurality of full wave rectifier circuitscoupled to the outputs of the conversion means, and a first transformerincluding a primary winding coupled to an output of the first invertercircuit and including a plurality of secondary windings coupled to thefull wave rectifier circuits; said conversion means further includesdrive means coupled to the first inverter circuit for operating it at aselected alternating rate substantially higher than the alternating rateof the incoming AC voltage on the input supply line to produce an ACvoltage at the output of the first inverter circuit; said power supplyincludes flux sensing means for sensing the flux in the firsttransformer; and said control circuit includes means responsive to theflux sensed in the first transformer for controlling the turn-on time ofthe controlled rectifier switches and thereby maintaining a constantflux density in the first transformer to regulate the output DC voltagesprovided at the outputs of the conversion means.
 7. A DC power supply asin claim 6 wherein said flux sensing means comprises: means coupled to asecondary winding of the first transformer for sensing the voltageacross the secondary winding in the unloaded condition with no loadcurrent flowing therein; and means for producing a feedback signal fromthe voltage sensed across the secondary winding of the first transformerto control the turn-on time of the controlled rectifier switches.
 8. ADC power supply as in claim 6 wherein: said conversion means includes asecond inverter circuit, and A second transformer having a primarywinding coupled to an output of the second inverter circuit and having aplurality of secondary windings coupled to the full wave rectifiercircuits; said drive means is coupled to the second inverter circuit foroperating it at the selected alternating rate to produce an AC voltageat the output of the second inverter circuit, the AC voltage produced atthe output of the second inverter circuit being out of phase withrespect to the AC voltage produced at the output of the first invertercircuit; said flux sensing means is operable for sensing the flux inboth the first and second tranformers; and said control circuit isresponsive to the flux sensed in the first and second transformers forcontrolling the turn-on time of the controlled rectifier switches andthereby maintaining a constant flux density in the first and secondtransformers to regulate the DC voltages provided at the outputs of theconversion means.
 9. A DC power supply as in claim 6 wherein saidcontrolled rectifier switches are SCR''s.